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| FUJITSU SEMICONDUCTOR DATA SHEET DS04-29121-1E Spread Spectrum Clock Generator MB88161 DESCRIPTION MB88161 is a clock generator for EMI (Electro Magnetic Interference) reduction. The peak of unnecessary radiation noise (EMI) can be attenuated by making the oscillation frequency slightly modulate periodically with the internal modulator. FEATURES * * * * * * * * * * * * Input frequency : 20 MHz to 28 MHz (Multiplied by 1), 14 MHz to 40 MHz (Multiplied by 2) Multiplication rate : 1, 2 Output frequency : 20 MHz to 28 MHz (Multiplied by 1), 28 MHz to 80 MHz (Multiplied by 2) Modulation rate : no modulation, 0.5%, 1.0%, 2.0%, - 1.0%, - 2.0%, - 4.0% (The terminal can be selected.) Equipped with oscillation circuit : Range of oscillation 10 MHz to 40 MHz Built-in oscillation stabilization capacitance : 4pF (Typ) Modulation clock output Duty : 40% to 60% Modulation clock Cycle-Cycle Jitter : Less than 100 ps Low current consumption by CMOS process : 7.0 mA (24 MHz : no load, Typ-sample, Typ-condition) Power supply voltage : 2.7 V to 3.6 V Operating temperature : - 40 C to + 85 C Package : BCC 18-pin PACKAGE 18-pin plastic BCC (LCC-18P-M05) MB88161 PIN ASSIGNMENT (TOP VIEW) NC NC NC NC S0 VSS SPRD OUT S1 15 14 13 12 11 10 16 17 18 1 2 NC 3 NC 4 NC 5 NC MB88161 9 8 7 6 OE XOUT XIN VDD MLTP PIN DESCRIPTION Pin no. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 Pin name S1 NC NC NC NC MLTP VDD XIN XOUT OE NC NC NC NC S0 VSS SPRD OUT I/O I I I O I I I O Description Modulation rate setting pin (with pull-up resistance) Non-connection pin (do not connect anything) Non-connection pin (do not connect anything) Non-connection pin (do not connect anything) Non-connection pin (do not connect anything) Multiplication rate setting pin (with pull-down resistance) Power supply voltage pin Resonator connection pin/clock input pin Resonator connection pin Clock output enable pin (with pull-up resistance) Non-connection pin (do not connect anything) Non-connection pin (do not connect anything) Non-connection pin (do not connect anything) Non-connection pin (do not connect anything) Modulation rate setting pin (with pull-up resistance) GND pin Modulation type setting pin (with pull-up resistance) Modulation clock output pin (OE= "L" Hi-Z output) 2 MB88161 I/O CIRCUIT TYPE Pin Circuit type 22 k OE signal Remarks * With pull-up resistor The value of pull-up resistor is switched by the input level of OE signal. 800 k at OE= "L" (Typ) 22 k at OE= "H" (Typ) * CMOS hysteresis input OE 800 k Note : At OE="L" 22k Pull Up cut 50 k OE signal S0, S1, SPRD * With pull-up resistor 50 k (Typ) * CMOS hysteresis input * Pull-up resistor is disconnected at OE= "L", and internal signal is fixed to "L". Note : At OE="L" Pull Up cut * With pull-down resistor 50 k (Typ) * CMOS hysteresis input * Pull-down resistor is disconnected at OE= "L", and internal signal is fixed to "L". MLTP OE signal 50 k Note : At OE="L" Pull Down cut OE signal * CMOS output * IOL = 8.0 mA * Hi-Z output at OE= "L" OUT Note : At OE="L" Hi-Z output (Continued) 3 MB88161 (Continued) Pin Circuit type Remarks * Oscillation circuit * Built-in feedback resistance : 500 k (Typ) * Built-in oscillation stabilization capacitance : 4 pF (Typ) XIN 4 pF XIN, XOUT XOUT 500 k 4 pF 4 MB88161 HANDLING DEVICES Preventing Latch-up A latch-up can occur if, on this device, (a) a voltage higher than power supply voltage or a voltage lower than GND is applied to an input or output pin or (b) a voltage higher than the rating is applied between power supply and GND. The latch-up, if it occurs, significantly increases the power supply current and may cause thermal destruction of an element. When you use this device, be very careful not to exceed the maximum rating. Handling unused pins Do not leave an unused input pin open, since it may cause a malfunction. Handle by, using a pull-up or pulldown resistor. Power supply pins Please design connecting the power supply pin of this device by as low impedance as possible from the current supply source. We recommend connecting electrolytic capacitor (about 10 F) and the ceramic capacitor (about 0.01 F) in parallel between power supply and GND near the device, as a bypass capacitor. Oscillation circuit Noise near the XIN pin and XOUT pin may cause the device to malfunction. Design printed circuit boards so that electric wiring of XIN pin or XOUT pin and the resonator do not intersect other wiring. Design the printed circuit board that surrounds the XIN pin and XOUT pin with ground. 5 MB88161 BLOCK DIAGRAM VDD OE Output enable Power Down Multiplication rate setting MLTP Modulation type setting SPRD Modulation rate setting PLL block Modulation rate setting Hi-Z control Modulation clock output OUT S0 S1 XOUT 4 pF Reference clock Power Down XIN Rf = 500 k 4 pF VSS 1 - M Phase compare Charge pump V/I conversion IDAC ICO Reference clock 1 - N Loop filter Modulation clock output 1 - L Modulation logic Modulation rate setting S0, S1 MB88161 PLL block A glitchless IDAC (current output D/A converter) provides precise modulation, thereby dramatically reducing EMI. 6 MB88161 PIN SETTING After the pin setting is changed, the stabilization wait time of the modulation clock is required. The stabilization wait time of the modulation clock takes the maximum value of Lock-Up time in "* AC Characteristics" in ELECTRICAL CHARACTERISTICS. Each setting pin contains the pull-up resistor or pull-down resistor. Therefore, these pins is set to default state for input opened. MLTP multiplication setting MLTP Multiplication rate L H Multiplied by 1 Multiplied by 2 Input Frequency 20 MHz to 28 MHz 14 MHz to 40 MHz Output Frequency 20 MHz to 28 MHz 28 MHz to 80 MHz Remarks Default Note : Set MLTP pin to "L" for input opened because MLTP pin has the pull-down resistor. OE clock output enable OE L H Status Modulation clock output (OUT pin) Hi-Z/Power down status Operation status Remarks Default Note : When OE pin is set to "L", all oscillation circuits/PLL stop and enter power down mode, low-power consumption mode. Modulation clock output (OUT pin) becomes Hi-Z state during the power down. Set OE pin to "H" for input opened because OE pin has the pull-up resistor. SPRD modulation type setting SPRD L H Modulation type Down spread Center spread Remarks Default Note : Set SPRD pin to "H" for input opened because SPRD pin has the pull-up resistor. S0/S1 modulation rate setting S1 L L H H S0 L H L H Modulation rate At down spread No modulation - 1.0% - 4.0% - 2.0% At center spread No modulation 0.5% 2.0% 1.0% Remarks Default Note : Set S1 pin and S0 pin to "H" for input opened because S1 pin and S0 pin have the pull-up resistor. 7 MB88161 * Center spread Spectrum is spread (modulated) by centering on the non-spread frequency. Radiation level Modulation width 2.0% -1.0% +1.0% Frequency Non-spread frequency Example of center spread modulation rate 1.0% * Down spread Spectrum is spread (modulated) below the non-spread frequency. Modulation width 2.0% Radiation level -2.0% Frequency Non-spread frequency Example of down spread modulation rate - 2.0% 8 MB88161 ABSOLUTE MAXIMUM RATINGS Parameter Power supply voltage* Input voltage* Output voltage* Storage temperature Operation junction temperature Output current Overshoot Undershoot Symbol VDD VI VO TST TJ IO VIOVER VIUNDER Rating Min - 0.5 VSS - 0.5 VSS - 0.5 - 55 - 40 - 14 Max + 4.0 VDD + 0.5 VDD + 0.5 + 125 + 125 + 14 VDD + 1.0 (tOVER 50 ns) Unit V V V C C mA V V VSS-1.0 (tUNDER 50 ns) * : The parameter is based on VSS = 0.0 V. WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings. Overshoot/Undershoot tUNDER 50 ns VIOVER VDD + 1.0 V VDD VSS tOVER 50 ns VIUNDER VSS - 1.0 V 9 MB88161 RECOMMENDED OPERATING CONDITIONS (VSS = 0.0 V) Parameter Power supply voltage "H" level input voltage "L" level input voltage Input clock duty cycle Operating temperature Symbol VDD VIH VIL tDCI Ta Pin VDD XIN, MLTP, OE, SPRD, S1, S0 XIN Conditions Input frequency 14 MHz to 40 MHz Value Min 2.7 VDD x 0.80 VSS 40 - 40 Typ 3.3 50 Max 3.6 VDD + 0.3 VDD x 0.20 60 + 85 Unit V V V % C WARNING: The recommended operating conditions are required in order to ensure the normal operation of the semiconductor device. All of the device's electrical characteristics are warranted when the device is operated within these ranges. Always use semiconductor devices within their recommended operating condition ranges. Operation outside these ranges may adversely affect reliability and could result in device failure. No warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet. Users considering application outside the listed conditions are advised to contact their FUJITSU representatives beforehand. Input clock duty cycle (tDCI = tb/ta) ta tb VDD x 0.8V IN VDD x 0.2V VDD x 0.5V 10 MB88161 ELECTRICAL CHARACTERISTICS * DC Characteristics (Ta = - 40 C to + 85 C, VDD = 2.7 V to 3.6 V, VSS = 0.0 V) Parameter Power supply current Power down current Symbol ICC IPD VOH Output voltage VOL Output impedance Load capacitance Built-in oscillation stabilization capacitance ZOC CL COSC RPUOEH RPUOEL Input pull-up resistance RPU Input pull-down resistance RPD OUT OUT XIN, XOUT OE OE OE, SPRD, S1, S0 MLTP OUT Pin VDD VDD Conditions 24 MHz output no load capacitance At power down (At OE="L") "H" level output, IOH= - 8 mA "L" level output, IOL = 8 mA 20 MHz to 80 MHz 20 MHz to 80 MHz Value Min 0.8 x VDD VSS 10 500 25 25 Typ 7.0 5 30 4 25 800 50 50 Max 11.0 20 VDD 0.2 x VDD 15 100 1200 200 200 Unit mA A V V pF pF k k k k VIH=0.8 x VDD VIL=0.0V VIL=0.0V VIH=VDD Note : When OE pin is set to "L", the pull-up resistor connected to SPRD pin, S1 pin, and S0 pin and the pull-down resistor connected to MLTP pin are disconnected, and internal signal is fixed to "L". See " I/O CIRCUIT TYPE" for details. 11 MB88161 * AC Characteristics (Ta = - 40 C to + 85 C, VDD = 2.7 V to 3.6 V, VSS = 0.0 V) Parameter Symbol Pin Conditions MLTP= "L" Crystal oscillation input MLTP= "H" Crystal oscillation input MLTP= "L" Fundamental oscillation MLTP= "H" Fundamental oscillation MLTP= "L" MLTP= "H" 0.2 x VDD to 0.8 x VDD Load capacitance 15pF 0.2 x VDD to 0.8 x VDD Load capacitance 15 pF 0.5 x VDD Input frequency at 24MHz Multiplied by 1 Input frequency at 24MHz Multiplied by 2 Ta= + 25C, VDD=3.3V, No load capacitance, Standard deviation 0.0V to 2.7V Rise time or fall time of "OE" at 5 ns Rise time or fall time of "OE" at 5 ns Rise time or fall time of "OE" at 5 ns Load capacitance 15 pF Value Min 20 14 20 14 20 28 0.4 0.4 40 1 100 0 Typ 32.0 21.3 4 Max 28 MHz 40 28 MHz 40 28 80 4.0 4.0 60 kHz 10 100 10 10 ms ps s s ns ns MHz ns ns % Unit Input frequency fin XIN Crystal oscillation frequency fx XIN, XOUT Output frequency Output clock rise time Output clock fall time Output clock duty cycle fOUT tr tf tDCC OUT OUT OUT OUT Modulation frequency fMOD OUT Lock-Up time Cycle-Cycle jitter Output enable "L" width Power supply rise time Output Hi-Z start time after power down entry Output Hi-Z release time after power down exit Output start time after power down exit tLK tJC tOELW tVDR tPEZ tPIZ OUT OUT OE VDD OUT OUT tPIO OUT ns Note : The stabilization wait time of the modulation clock is required after the power is turned on or when the clock output enable setting (OE pin), multiplication setting (MLTP pin) or modulation rate setting (S1pin and S0 pin) is changed. The stabilization wait time of the modulation clock takes the maximum value of Lock-Up time. 12 MB88161 OUTPUT CLOCK DUTY CYCLE (tDCC = tb/ta) ta tb VDD x 0.8V OUT VDD x 0.2V VDD x 0.5V INPUT FREQUENCY (fin = 1/tin) tin VDD x 0.8V VDD x 0.2V XIN OUTPUT CLOCK RISE TIME/OUTPUT CLOCK FALL TIME (tr/tf) VDD x 0.8V OUT tr VDD x 0.2V tf CYCLE-CYCLE JITTER (tJC = | tn - tn+1 |) OUT tn tn+1 Note : Cycle-cycle jitter indicates the difference between a certain cycle and the immediately succeeding (or preceding) cycle. 13 MB88161 OUTPUT ENABLE "L" WIDTH (tOELW) tOELW OE VDD x 0.8V VDD x 0.2V POWER SUPPLY RISE TIME (tVDR) tVDR 2.7V VDD 0.0V OUTPUT Hi-Z START TIME AFTER POWER DOWN ENTRY (tPEZ) OE VDD x 0.2V tPEZ OUT Hi-Z OUTPUT Hi-Z RELEASE TIME * OUTPUT START TIME AFTER POWER DOWN EXIT (tPIZ * tPIO) VDD x 0.8V OE tPIO tPIZ OUT Hi-Z VDD x 0.2V 14 MB88161 MODULATION WAVEFORM * Modulation rate 1.0%, example of center spread OUT output frequency + 1.0 % Frequency at modulation OFF Time - 1.0 % fMOD = 32 kHz (Typ) * Modulation rate -2.0%, example of down spread OUT output frequency Frequency at modulation OFF Time - 2.0 % fMOD = 32 kHz (Typ) 15 MB88161 LOCK-UP TIME VDD 2.7 V Oscillation stabilization wait time XIN OE VIH VIH Setting pin S1, S0, MLTP, SPRD OUT tLK (lock-up time ) The clock stabilization wait time is required when the power is turned on. If the OE pin is fixed at "H" level, the maximum time after the power is turned on until the required clock is obtained is (the stabilization wait time of input clock to XIN pin) + (the lock-up time "tLK") . For the stabilization wait time of input clock to the XIN pin, check the characteristics of the resonator or oscillator used. VDD 2.7 V Oscillation stabilization wait time XIN OE VIH Setting pin S1, S0, MLTP, SPRD OUT VIH tLK (lock-up time ) If the OE pin is used for power down control, the required clock is obtained at most the lock-up time "tLK" after the OE pin goes "H" level. 16 MB88161 XIN OE VIH VIH Setting pin S1, S0, MLTP, SPRD OUT VIL tLK (lock-up time ) tLK (lock-up time ) If the setting pin (S1, S0, MLTP, or SPRD) is used for control during normal operation, the required clock is obtained at most the lock-up time "tLK" after the level at the pin is determined. Note : The wait time for the clock signal output from the OUT pin to become stable is required after the IC is released from power-down mode by the OE pin or after another pin's setting is changed. During the period until the output clock signal becomes stable, the output frequency, output clock duty cycle, modulation period, and Cycle-Cycle jitter characteristic cannot be guaranteed. It is therefore advisable to perform processing such as cancelling a reset of the device at the succeeding stage after the lock-up time. 17 MB88161 CRYSTAL OSCILLATION CIRCUIT The figure below shows the connection example about general crystal resonator. The oscillation circuit has the built-in feedback resistor (500k) and oscillation stabilization capacitance (4 pF). Because the value of oscillation stabilization capacitance must be adjusted to the most suitable value of individual oscillator, add the capacitance (C1 and C2) to LSI external if necessary. 4 pF Rf (500k) 4 pF LSI Internal XIN Pin XOUT Pin LSI External C1 C2 INTERCONNECTION CIRCUIT EXAMPLE S0 15 14 13 12 11 10 VSS SPRD OUT S1 1 R1 2 3 4 5 6 16 17 18 MB88161 9 8 7 XOUT XIN VDD OE MLTP + C1 C2 C4 C3 C1, C2 C3 C4 R1 : Oscillation stabilization capacitance (see " CRYSTAL OSCILLATION CIRCUIT".) : Capacitor of 10 F or higher : Capacitor of about 0.01 F (connect a capacitor of good high frequency property (ex. laminated ceramic capacitor) to close to this device) : Impedance matching resistor for board pattern 18 MB88161 ORDERING INFORMATION Part no. MB88161PVB-G-EFE1 MB88161PVB-G-ERE1 Package 18-pin plastic BCC (LCC-18P-M05) Emboss taping EF type ER type 19 MB88161 PACKAGE DIMENSION 18-pin plastic BCC (LCC-18P-M05) 2.700.10 (.106.004) 0.450.05 (.018.002) (Mount height) 2.31(.090) TYP 0.45(.018) TYP. 15 10 10 15 INDEX AREA 2.400.10 (.094.004) 2.01(.079) TYP 0.45(.018) TYP. 0.0750.025 (.003.001) (Stand off) "A" "C" "B" 0.90(.035) REF 1.90(.075) REF 1 6 6 1.35(.053) REF 2.28(.090) REF 1 Details of "A" part 0.05(.002) 0.14(.006) MIN. 0.250.06 (.010.002) Details of "B" part C0.10(.004) 0.360.06 (.014.002) Details of "C" part 0.360.06 (.014.002) 0.250.06 (.010.002) 0.280.06 (.011.002) 0.280.06 (.011.002) C 2003 FUJITSU LIMITED C18058S-c-1-1 Dimensions in mm (inches) Note: The values in parentheses are reference values. 20 MB88161 FUJITSU LIMITED All Rights Reserved. The contents of this document are subject to change without notice. Customers are advised to consult with FUJITSU sales representatives before ordering. The information, such as descriptions of function and application circuit examples, in this document are presented solely for the purpose of reference to show examples of operations and uses of Fujitsu semiconductor device; Fujitsu does not warrant proper operation of the device with respect to use based on such information. When you develop equipment incorporating the device based on such information, you must assume any responsibility arising out of such use of the information. Fujitsu assumes no liability for any damages whatsoever arising out of the use of the information. Any information in this document, including descriptions of function and schematic diagrams, shall not be construed as license of the use or exercise of any intellectual property right, such as patent right or copyright, or any other right of Fujitsu or any third party or does Fujitsu warrant non-infringement of any third-party's intellectual property right or other right by using such information. Fujitsu assumes no liability for any infringement of the intellectual property rights or other rights of third parties which would result from the use of information contained herein. The products described in this document are designed, developed and manufactured as contemplated for general use, including without limitation, ordinary industrial use, general office use, personal use, and household use, but are not designed, developed and manufactured as contemplated (1) for use accompanying fatal risks or dangers that, unless extremely high safety is secured, could have a serious effect to the public, and could lead directly to death, personal injury, severe physical damage or other loss (i.e., nuclear reaction control in nuclear facility, aircraft flight control, air traffic control, mass transport control, medical life support system, missile launch control in weapon system), or (2) for use requiring extremely high reliability (i.e., submersible repeater and artificial satellite). Please note that Fujitsu will not be liable against you and/or any third party for any claims or damages arising in connection with above-mentioned uses of the products. Any semiconductor devices have an inherent chance of failure. You must protect against injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating conditions. If any products described in this document represent goods or technologies subject to certain restrictions on export under the Foreign Exchange and Foreign Trade Law of Japan, the prior authorization by Japanese government will be required for export of those products from Japan. F0602 (c) 2006 FUJITSU LIMITED Printed in Japan |
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